Author: ABILASHA U R, MTech 2nd Year, Digital Electronics & Communications Department

College: MVJ college of engineering, Banglore.

The Proposed algorithm is modelled in Verilog HDL and simulated using Xilinx ISE Design tool for QPSK(Ncbps = 96) , 16-QAM(Ncbps = 192), 64-QAM (Ncbps = 576). The design was implemented on SPARTAN 3 Xilinx FPGA (Device XC3S500E) and tested successfully for QPSK,16-QAM and 64-QAM.

KEYWORDS: WiMAX(interleaver and de-interleaver), IEEE 802.16e standard, modulation techniques, Feild Programmable gate Arrays(FPGA).

IEEE 802.16 is a solution to broadband wireless access (BWA) commonly known as Worldwide Interoperability for Microwave Access (WiMAX), is a recent wireless broadband standard that has promised high bandwidth over long-range transmission. Broadband wireless access (BWA) systems have evolved as the solution for the persistent demand of these multimedia services [1]. It provides enhancement in multimedia data services and quality of service (QoS). It support simultaneous voice, data and multimedia services to a large group of subscribers without the need for digital subscriber line (DSL) or cable modem. WLAN and WiMAX are emerging standards for wireless broadband communication system. WiMAX is an emerging industry consortium standard for wireless broadband networking. It is based on wireless metropolitan area networking (WMAN) standards. It offers a rich set of features with a lot of flexibility in terms of deployment options and potential service offerings. The WiMAX physical layer (PHY) is based on orthogonal frequency division multiplexing which offers good resistance to multipath and allows WiMAX to operate in Non Line of Site (NLOS) conditions.

The direct implementation of interleaver/deinterleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver/deinterleaver functions which reduces the overall hardware complexity to compute the deinterleaver addresses and also eliminates the requirement of floor function is proposed[6],

WiMAX implemented on FPGA can easily be upgraded by making necessary changes in the Hardware Description Language (HDL) code. In addition FPGA based circuit is much shorter compared to Application Specific Integrated Circuit (ASIC). Design flexibility is another important advantage of FPGA based implementation.

In this brief, use of FPGA’s embedded multiplier provides performance improvement by reducing interconnection delay, efficient resource utilization, and lesser power consumption compared with a configurable logic block-based multiplier. Our work shows betterment over the LUT technique to the tune of approximately 49% in terms of maximum operating frequency.

The system level overview of IEEE 802.16e based WiMAX system is described in Fig.1. In this system, the input binary data stream obtained from a source is randomized to prevent a long sequence of 1s and 0s, which will cause timing recovery problem at the receiver. Psudeo Random Binary Sequence (PRBS) is used in which randomization is done by modulo 2 addition of the data with the output of the PBRS itself . The randomized data bits are there after encoded using Reed Solomon (RS) encoder followed by Convolutional Coder (CC). The former is suitable for correction of burst type of error whereas the later is for random error. After RS-CC encoding all encoded data bits shall be interleaved by a block interleaver.


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Certain Portions of the Article are Removed From this article due to plagiarism Complaint.